This invention relates to a timing system that is more particularly described as a timing system for distributing clock signals in a processing system having plural processing sections.
In the prior art, operation of a synchronous system is timed by a signal from a central clock. When some particular operation requires timing that is different than the central clock signal timing, another clock signal is derived at the central location from the central clock signal. To accommodate a large plurality of different particular operations which can occur in a synchronous system, many different clock signals are derived at the central location from the central clock signal. Typically all of these many clock signals are transmitted to all of the processing sections of the system by way of as many different clock leads as there are different clock signals.
A problem arises when a synchronous system includes many circuits in a small area such as in a very large scale integrated (VLSI) circuit. It is desirable to supply all of the needed clock signals to all of the processing sections of the integrated circuit chip while utilizing a minimum of chip area for distributing the many different clock signals. The problem is that the many clock leads occupy too much of the total area available for circuitry.